The exponential growth in integrated device density has yielded high-performance microprocessors containing almost 1 billion transistors per chip for the current 65 nm technology. Continuous scaling of the devices and performance requires innovations in materials, processes, and designs for both back-end-of-line (BEoL) interconnects and packaging structures. Mechanical reliability has been a limiting factor for implementation of new materials and processes.

Since 1997, copper (Cu) has been selected as the interconnect material to replace aluminum (Al) for two major reasons: (1) Cu has a lower electrical resistivity than Al, thus reducing the R-part of RC delay; (2) Cu has a higher melting point than Al, thus reducing diffusional creep and related reliability concerns such as stress migration and electromigration. However, implementation of Cu interconnects required new processes, such as Cu electroplating, damascene processes, and chemical-mechanical planarization (CMP), which led to a series of new reliability issues. At the 90 nm technology node (around 2002), dielectric materials with k (relative dielectric constant) lower than silicon dioxide (SiO2, k ~ 4) were implemented into the Cu interconnects, to reduce the C-part of RC delay. Implementation of low k dielectrics has posed even more challenges for at least three reasons: (1) There are many possible new materials, but no clear winner; (2) Most of low k materials are mechanically weak (low modulus, low fracture toughness); and (3) Integration of low k materials with other materials is difficult due to large mismatch in thermal expansion coefficients and poor adhesion. As the technology advances, the interconnect structure continues to evolve with decreasing dimensions and increasing complexity in materials and structures. At this time, the effort of the microelectronics industry is focused on implementing ultra-low k porous dielectric materials (k < 2.5) into Cu interconnects to further reduce the RC delay. Meanwhile, the packaging technology for advanced integrated circuits has also been evolving, with the implementation of plastic substrates along with multilayered high-density wiring and solder balls in flip-chip packages. The environmental safety mandates the change from Pb-based solders to Pb-free solders, which are more prone to thermal cyclic fatigue and electromigration reliability problems.

Traditionally, reliability problems for BEoL interconnects and packaging are addressed separately, due to different materials, processes, and dimensions. Recently it is found that Cu/low k interconnects often fail after incorporating the silicon dies into plastic flip-chip packages, raising the concern of chip-package interaction (CPI) as a critical reliability challenge. Different from a stand-alone silicon die, the thermal deformation of the packaging structure can be directly coupled into the Cu/low k interconnects, inducing large local stresses to drive fracture and delamination (see figure below). Depending on the solder materials, the reflow temperature is about 160°C for eutectic Pb alloys and about 250°C for Sn-based Pb-free solders. During accelerated or cyclic thermal tests, the temperature varies from 25°C to 125°C or 150°C. Although the assembly or test temperatures of the package are considerably lower than the chip processing temperatures, chip-package interaction can induce very different stresses in the interconnect structures, due to the mismatch of the coefficients of thermal expansion (CTEs) between the chip (3 ppm/°C for Si) and the packaging substrate (17 ppm/°C for a plastic substrate). The thermally induced shear stress on the solder balls reaches a maximum at the outermost solder row and increases with the size of the chip. Use of the underfill effectively reduces the shear stress, but causes the package to warp, resulting in large peeling stresses at the die-underfill and die-solder interfaces.

The challenge to address CPI-induced reliability issues lies in all areas, from modeling, designing, to manufacturing and testing. Since CPI-induced failure occurs only after package assembling processes of Si dies containing Cu/low k interconnects, the cycle of trial-and-error (make-and-break) can be long and expensive. Finite element based modeling along with fracture mechanics based reliability analysis has been developed for understanding the impact of CPI on reliability of Cu/low k interconnects. However, grant challenges lie ahead for quantitatively faithful modeling as a guide for optimal design of the interconnect and packaging structures. These include: (1) large difference in dimensions from the packaging level (10^(-2) -10^(-3) m) to the interconnect level (10^(-8) m); (2) complex three-dimensional integrated architecture; (3) diverse materials, often with not well characterized thermomechanical properties; (4) uncertainties in crack nucleation and propagation conditions. Here is a recent review on the current approaches of modeling and experiments as well as the current understanding of the CPI effect . A more focused reference is attached below:

• G. Wang, P. S. Ho and S. Groothuis, “Chip-packaging interaction: a critical concern for Cu/low k packaging”, Microelectronics Reliability 45, 1079-1093 (2005).

One practical approach to preventing CPI induced cracking is to incorporate patterned metal structures around the chip perimeter as a crack stop. Both modeling and experimental measurement of the effective toughness of crack stop structures are critical for the design and reliability. Researchers at IBM TJ Watson Research Center presented their work at the 2007 International Interconnect Technology Conference (IITC), which is summarized in the following paper:

• T. M. Shaw, E. Liniger, G. Bonilla, J. P. Doyle, B. Herbst, X. H. Liu, M. W. Lane,  “Experimental determination of the toughness of crack stop structures”, Proc. IEEE International Interconnect Technology Conference, pp. 114-116 (2007).

Beyond the Cu/low k technology, two technology innovations are on the horizon and currently under investigation. First, to further reduce the RC delay, implementation of air-gaps in the trench dielectric levels has been demonstrated as a potential solution (e.g., an IBM air-gap structure ). However, it remains a challenging problem to design and fabricate air-gap interconnect structures with satisfactory reliability at an acceptable cost. Collapse of bridging low k cap (or hard mask) over wide air gaps has been observed during thermal decomposition of gap forming materials. The keyhole shaped air gaps by etchback and non-conformal refill schemes may behave as sites of stress concentration, thus prone to cracking. As packaging assembly exerts additional stresses to the fragile air-gap structures, chip-package interaction may cause more serious reliability issues. An introduction to the integration and reliability issues of air-gap interconnect structures is attached here:

• R. Hoofman, R. Daamen, J. Michelon, V. Nguyenhoang, “Alternatives to low-k nanoporous materials: dielectric air-gap integration”, Solid State Technology 49, 55-58 (2006).

Further down the technology roadmap, three-dimensional (3D) integration of interconnects and packaging is being considered to dramatically enhance chip performance, functionality, and device density (see figure for an illustration). Researchers at IBM and IMEC are leading the way investigating key technology challenges of 3D architectures; two of their papers are attached below. Mechanical reliability remains to be a critical issue, and chip-package interaction becomes inherently relevant for 3D integration. New reliability challenges include: mechanical ramification of high-aspect ratio through-silicon vias (TSVs), handling of dramatically thinned silicon dies, alignment and bonding among stacked wafers, among others. The role of mechanics in the development of 3D technology is yet to be established.

• W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, “Three-dimensional integrated circuits ”, IBM Journal of Research and Development 50, 491-506 (2006).
• P. De Moor, W. Ruythooren, P. Soussan, B. Swinnen, K. Baert, C. Van Hoof, and E. Beyne, “Recent advances in 3D integration at IMEC”, Mater. Res. Soc. Symp. Proc. 970, No. 0970-Y01-02 (2006).