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Jun He's picture

Materials Impact on Interconnects Process Technology and Reliability

M.A. Hussein and Jun He (Intel Corporation)

IEEE Transactions on Semiconductor Manufacturing, vol. 18, No. 1, p.69-85, 2005

In this work, we explain how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper, as the metal of choice at the 130nm technology node, mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of the interconnect system. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing, pose serious challenges to the implementation of such materials in high volume manufacturing. We will consider the cases of two ILD materials; carbon-doped silicon dioxide (CDO) and low-k spin-on-polymer to illustrate the impact of ILD choice on the process technology and reliability of copper interconnects. preprint pdf 2.49 MB

Jie-Hua Zhao's picture


Flip-chip plastic ball grid array (FC-PBGA) packages are widely used in high performance components. However, its die back is normally under tensile stress at low temperatures. This paper presents a probabilistic mechanics approach to predict the die failure rate in the FC-PBGA qualification process. The methodology consists of three parts:

Jie-Hua Zhao's picture

Microstructure-based Stress Modeling of Tin Whisker Growth

Jie-Hua Zhao, Peng Su, Min Ding, Sheila Chopin, and Paul S. Ho

A 3-dimensional finite element method (FEM) model considering the elasticity anisotropy, thermal expansion anisotropy and plasticity of β-Sn is established. The Voronoi diagrams are used to generate the geometric patterns of grains of the Sn coating on Cu leadframes. The crystal orientations are assigned to the Sn grains in the model using the x-ray diffraction (XRD) measurement data of the samples. The model is applied to the Sn-plated package leads under thermal cycling tests. The strain energy density (SED) is calculated for each grain. It is observed that the samples with higher calculated SED are more likely to have longer Sn whiskers and higher whisker density. The FEM model, combined with the XRD measurement of the Sn finish, can be used as an effective indicator of the Sn whisker propensity. This may expedite the qualification process significantly.

Joost Vlassak's picture

The Effect of Water Diffusion on the Adhesion of Organosilicate Glass Film Stacks

Ting Y. Tsui, Andrew J. McKerrow, and Joost J. Vlassak

Published in the Journal of The Mechanics and Physics of Solids, 54 (5), 887-903 (2006)

Abstract – Organosilicate glass (OSG) is a material that is used as a dielectric in advanced integrated circuits. It has a network structure similar to that of amorphous silica where a fraction of the Si-O bonds has been replaced by organic groups. It is well known from prior work that OSG is sensitive to subcritical crack growth as water molecules in the environment are transported to the crack tip and assist in rupturing Si-O bonds at the crack tip. In this study, we demonstrate that exposure of an OSG containing film stack to water prior to fracture results in degradation of the adhesion of the film stack. This degradation is the result of the diffusion of water into the film stack. We propose a quantitative model to predict adhesion degradation as a function of exposure time by coupling the results of independent subcritical crack growth measurements with diffusion concentration profiles. The model agrees well with experimental data and provides a novel method for measuring the water diffusion coefficient in film stacks that contain OSG. This study has important implications for the reliability of advanced integrated circuits.

Question about dislocation nucleation sites in strained silicon-on-insulator

Electronic active device is built on the strained silicon-on-insulator (sSOI), e.g. strained Si layer on oxide, which in turn is bonded on bulk silicon wafer. Because no misfit dislocation can exist in strained silicon layer any more, will the dislocation be generated during later processing and operation? If there are still lots of dislocations in the strained silicon layer, where do they come from? Is there any experimental work to discover the dislocation nucleation sites? I guess they will nucleate from the triple junctions of gate-sSOI-cap, because the stress is singular in the triple junction. But I am not sure. So I want to know something about the experimental observations.

Zhigang Suo's picture

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