By Martijn Feron, Zhen Zhang and Zhigang Suo

The mobility of charge carriers in silicon can be significantly increased when silicon is subject to a field of strain.In a microelectronic device, however, the strain field may be intensified at a sharp feature, such as an edge or a corner, injecting dislocations into silicon and ultimately failing the device. The strain field at an edge is singular, and is often a linear superposition of two modes of different exponents. We characterize the relative contribution of the two modes by a mode angle, and determine the critical slip systems as the amplitude of the load increases. We calculate the critical residual stress in a thin-film stripe bonded on a silicon substrate.

In practice, the SiN stripes or pads are periodically patterned on silicon, so the spacing effect on dislocation injection from sharp features deserves attention. As in Figure 1, the SiN stripes with residue stress , of width L and thickness h, are periodically patterned with spacing S. In the numerical calculation, we take shear modulus and Poisson’s ratio of Si3N4 to be 54.3 GPa and 0.27, and those of silicon 68.1GPa and 0.22, the same as in Ref.[1].

Stresses inevitably arise in a microelectronic device due to mismatch in coefficients of thermal expansion, mismatch in lattice constants, and growth of materials. Moreover, in the technology of strained silicon devices, stresses have been deliberately introduced to increase carrier mobility. A device usually contains sharp features like edges and corners, which may intensify stresses, inject dislocations into silicon, and fail the device. On the basis of singular stress fields near the sharp features, this letter describes a method to obtain conditions that avert dislocations.

Electronic active device is built on the strained silicon-on-insulator (sSOI), e.g. strained Si layer on oxide, which in turn is bonded on bulk silicon wafer. Because no misfit dislocation can exist in strained silicon layer any more, will the dislocation be generated during later processing and operation? If there are still lots of dislocations in the strained silicon layer, where do they come from? Is there any experimental work to discover the dislocation nucleation sites? I guess they will nucleate from the triple junctions of gate-sSOI-cap, because the stress is singular in the triple junction. But I am not sure. So I want to know something about the experimental observations.