Stretchable zigzag interconnects have potential applications in dynamic environments and in some biological systems.

Stretchability of metal interconnects over polymer substrates (elastomer in particular) have been discussed in detail in the following papers:

Jeannette M. Jacques, Ting Y. Tsui, Andrew J. McKerrow, and Robert Kraft

To improve capacitance delay performance of the advanced back-end-of-line (BEOL) structures, low dielectric constant organosilicate glass (OSG) has emerged as the predominant choice for intermetal insulator. The material has a characteristic tensile residual stress and low fracture toughness. A potential failure mechanism for this class of low-k dielectric films is catastrophic fracture due to channel cracking. During fabrication, channel cracks can also form in a time-dependent manner due to exposure to a particular environmental condition, commonly known as stress-corrosion cracking. Within this work, the environmental impacts of pressure, ambient, temperature, solution pH, and solvents upon the channel cracking of OSG thin films are characterized. Storage under high vacuum conditions and exposure to flowing dry nitrogen gas can significantly lower crack propagation rates. Cracking rates experience little fluctuation as a function of solution pH; however, exposure to aqueous solutions can increase the growth rate by three orders of magnitude.

One of the most common forms of cohesive failure observed in brittle thin film subjected to a tensile residual stress is channel cracking, a fracture mode in which through-film cracks propagate in the film. The crack growth rate depends on intrinsic film properties, residual stress, the presence of reactive species in the environments, and the precise film stack. In this paper, we investigate the effect of various buffer layers sandwiched between a brittle carbon-doped-silicate (CDS) film and a silicon substrate on channel cracking of the CDS film. The results show that channel cracking is enhanced if the buffer layer is more compliant than the silicon substrate. Crack velocity increases with increasing buffer layer thickness and decreasing buffer layer stiffness. This is caused by a reduction of the constraint imposed by the substrate on the film and a commensurate increase in energy release rate. The degree of constraint is characterized experimentally as a function of buffer layer thickness and stiffness, and compared to the results of a simple shear lag model that was proposed previously. The results show that the shear lag model does not accurately predict the effect of the buffer layer. (J. Mater. Res., Vol. 20, No. 9, Sep 2005)

See this post.

M.A. Hussein and Jun He (Intel Corporation)

IEEE Transactions on Semiconductor Manufacturing, vol. 18, No. 1, p.69-85, 2005

In this work, we explain how the manufacturing technology and reliability for advanced interconnects is impacted by the choice of metallization and interlayer dielectric (ILD) materials. The replacement of aluminum alloys by copper, as the metal of choice at the 130nm technology node, mandated notable changes in integration, metallization, and patterning technologies. Those changes directly impacted the reliability performance of the interconnect system. Although further improvement in interconnect performance is being pursued through utilizing progressively lower dielectric constant (low-k) ILD materials from one technology node to another, the inherent weak mechanical strength of low-k ILDs and the potential for degradation in the dielectric constant during processing, pose serious challenges to the implementation of such materials in high volume manufacturing. We will consider the cases of two ILD materials; carbon-doped silicon dioxide (CDO) and low-k spin-on-polymer to illustrate the impact of ILD choice on the process technology and reliability of copper interconnects. preprint pdf 2.49 MB