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Integrated Structures

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Journal Club Theme of March 15: Impact of Chip-Package Interaction on Reliability of Copper/Low k Interconnects and Beyond

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The exponential growth in integrated device density has yielded high-performance microprocessors containing almost 1 billion transistors per chip for the current 65 nm technology. Continuous scaling of the devices and performance requires innovations in materials, processes, and designs for both back-end-of-line (BEoL) interconnects and packaging structures. Mechanical reliability has been a limiting factor for implementation of new materials and processes.

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Influence of Interfacial Delamination on Channel Cracking of Brittle Thin Films


H. Mei, Y. Pang, and R. Huang, International Journal of Fracture 148, 331-342 (2007).

Following a previous effort published in MRS Proceedings, we wrote a journal article of the same title, with more numerical results. While the main conclusions stay the same, a few subtle points are noted in this paper.

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ASME Technical Committee on Integrated Structures

In response to a proposal by Zhigang Suo in November 2005, the Executive Committee of the Applied Mechanics Division (AMD) of ASME has created a new Technical Committee on Integrated Structures. The main purpose is to provide a home at AMD for those who are working in the interdisciplinary areas involving applied mechanics and integrated materials/structures such as microelectronics and biomedical technologies. Read more here.

To forge the link between academia and industries, the committee will be co-chaired by industrial and academic members. For the first year, Jun He of Intel and Rui Huang (myself) have served as the co-chairs. As the 2006 ASME Congress (November 5-10) coming around the corner, we would like to draw your attention to our first activities at the congress.

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