ES 240 Project: Stress in Flip-Chip Solder Bumps due to Semiconductor Die Warpage

Matt,

This sounds very interesting; I wasn't aware that this sort of force was generated in traces.  While I know relatively little about the area, you may benefit from the following two experimental papers.  You could try to reproduce their results numerically if you want to perform a sanity check on your results.  It might be valuable to vet your approach with real-world results.

-Tom

 http://link.aip.org/link/?JAPIAU/73/3790/1

 http://link.aip.org/link/?APPLAB/74/2945/1

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It’s an interesting project that studies one of the
important issues of microelectronic devices. It would be great to see how the
thermal stress profile will appear with temperature change during operation. I
have a couple of comments from one of the reference in the proposal [1] and
would like to suggest two potentially interesting references [2-3].

According to the paper by Prof. Tu, electromigration is
enhanced by tension but retarded by compression at the cathode and it is vice
versa at the anode. So, he suggests that “a favorable condition should be the
electron current entering the joint from the compression region and leaving
from the tension region.” [1] Thus, it would be interesting to find the tension
and compression regions at both cathode and anodes from the numerical
calculation which can be potentially useful for utilizing the effects that the
author mentioned. In addition, as the author mentioned, it would be also
interesting how the back stress, which can be built up in a flip chip solder
joint for the case of underfill, may interact with thermal shear stress.

As I search literatures about thermal stress in
solder-joint, I found two papers which can be helpful references. Wu et al. studied
the thermal stress in a Sn3.5AgCu half-bump solder joint under a
current stressing [2]. They reported substantial thermal stress accumulation around
the Al-to-solder interface, with a maximum stress of 138 MPa and the stress
gradient in the Ni layer of 1.67´1013 Pa/m resulting in a
stress migration force of 1.82´10−16 N, which is
comparable to the electromigration force, 2.82´10−16 N. In addition, Liu
et al. did 3D modeling of electromigration in IC device and solder joint (SnPb and SnAgCu lead-free solder materials) under the
combination of high current density, thermal load and mechanical load [3]. They
calculated the temperature, stress, atomic flux distribution in a packaging and
predicted void formation.

As a last comment, after doing thermal stress calculation, if
possible, it would be great to compare the numerical analysis result with the
experimental result for better understanding of the phenomena happening in the
flip-chip solder bumps during operation. 
 

References

[1] K. N. Tu, “Recent advances on
electromigration in very-large-scale integration of interconnects”, J. Appl.
Phys. 94, 5451 (2003).

[2] B. Y. Wu, Y. C.
Chan, and H. W. Zhong, M. O. Alam, J. K. L. Lai, “Study of the thermal stress in a Pb-free half-bump solder joint under
current stressing”, Appl. Phys. Lett. 90, 232112 (2007).

[3] Y. Liu, L. Liang, S. Irving, T. Luk “3D Modeling of electromigration
combined with thermal–mechanical effect for IC device and package”,
Microelectron. Reliab. 48, 811 (2008).