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FEA engineer job position in Microsoft, Mountain View, CA

Finite Element Analysis (FEA) and test data
analysis Engineer Job Description:


is a world leader in the design of entertainment devices. We are looking for a
creative, talented and experienced Finite Element Analysis (FEA) and test data
analysis Engineer.


Reliability Engineers Job Positions in Microsoft Hardware

There are many job positions on hardware reliability due to the success of on xbox Kinect. The following is the typical description. Please check out for more.

Reliability Engineer, Senior-IEB-MSCIS (740985) Job

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FEA Improves Reliability of Flip-Chip Packaging

On Aug 10, 2009, Semiconductor International (SI) Newsbreak published a report on my work in AMD about 3D fracture study of underfill delamination as the top story in that issue.  I have never imagined that. Except the pleasure I received from this good news, I wonder if this work is also interesting to iMechanica community.  For that reason, I attach here the SI news report and the original paper published on ITherm2008 Proceedings. Welcome any comments and thoughts.

How about "Rejecta Mechanica"?

A friend just forwarded me the following link:



Rejecta Mathematica is a new, open access, online journal that publishes only papers that have been rejected from peer-reviewed journals (or conferences with comparable review standards) in the mathematical sciences. We are currently seeking submissions for our inaugural issue.
About Rejecta Mathematica

Chip-package interaction and interfacial delamination

In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and services. The concentrated stresses result in delamination on many interfaces on several levels of structures, in various length scales from tens of nanometers to hundreds of micrometers. A major challenge to model flip-chip packages is the huge variation of length scales, the complexity of microstructures, and diverse materials properties. In this paper, we simplify the structure to be silicon/substrate with wedge configuration, and neglect the small local features of integrated circuits. This macroscopic analysis on package level is generic with whatever small local features, as long as the physical processes of interest occur in the region where the concentrated stress field due to chip-packaging interaction dominates. Because it is the same driving force that motivates all of the flaws. Therefore, the different interface cracks with same size and same orientation but on different interfaces should have similar energy release rates provided that the cracks are much smaller than the macroscopic length. We calculate the energy release rate and the mode angle of crack on the chip-package interface based on the asymptotic linear elastic stress field. In a large range of crack length, the asymptotic solution agrees with finite element calculation very well. We discuss the simplified model and results in context of real applications. In addition, we find that the relation of energy release rate G and crack length a is not power-law since local mode mixity is dependent of crack length a. Therefore, the curve of G~a can be wavy and hardly goes to zero even if crack length a goes to atomically small. The local mode mixity plays an important role in crack behavior.

A method to analyze dislocation injection from sharp features in strained silicon structures

Stresses inevitably arise in a microelectronic device due to mismatch in coefficients of thermal expansion, mismatch in lattice constants, and growth of materials. Moreover, in the technology of strained silicon devices, stresses have been deliberately introduced to increase carrier mobility. A device usually contains sharp features like edges and corners, which may intensify stresses, inject dislocations into silicon, and fail the device.

Want papers published, proposals granted and to be a good reviewer? Here is the key --- "Ten Simple Rules" series.

Getting papers published and getting proposals granted are often great challeges for young researchers, let alone being a good reviewer. The "Ten Simple Rules" series by P.E. Bourne, L.M. Chalupa, and A. Korngreen delineate what we should follow.

More details about writing a good paper and proposal were also given by G. M. Whitesides ("writing a paper") and M.F. Ashby ("how to write a paper").

Nanotube 'forest' makes super slippery surface

A material less sticky than Teflon has been created by covering a surface with a "forest" of carbon nanotubes. has a very interesting report. Read more...

Question about dislocation nucleation sites in strained silicon-on-insulator

Electronic active device is built on the strained silicon-on-insulator (sSOI), e.g. strained Si layer on oxide, which in turn is bonded on bulk silicon wafer. Because no misfit dislocation can exist in strained silicon layer any more, will the dislocation be generated during later processing and operation? If there are still lots of dislocations in the strained silicon layer, where do they come from? Is there any experimental work to discover the dislocation nucleation sites? I guess they will nucleate from the triple junctions of gate-sSOI-cap, because the stress is singular in the triple junction. But I am not sure. So I want to know something about the experimental observations.

My research work

I use this blog entry to upload my research work, then I have links for my publications in my resume. Otherwise, I don't have any links for my preprints.

If people can upload any files without writing a blog entry, that will be great.

Saturated voids in interconnect lines due to thermal strains and electromigration

Zhen Zhang, Zhigang Suo, Jun He

Thermal strains and electromigration can cause voids to grow in conductor lines on semiconductor chips. This long-standing failure mode is exacerbated by the recent introduction of low-permittivity dielectrics. We describe a method to calculate the volume of a saturated void (VSV), attained in a steady state when each point in a conductor line is in a state of hydrostatic pressure, and the gradient of the pressure along the conductor line balances the electron wind. We show that the VSV will either increase or decrease when the coefficient of thermal expansion of the dielectric increases, and will increase when the elastic modulus of the dielectric decreases. The VSV will also increase when porous dielectrics and ultrathin liners are used. At operation conditions, both thermal strains and electromigration make significant contributions to the VSV. We discuss these results in the context of interconnect design.

This has been published and the related references are listed here:

  • Z. Zhang, Z. Suo, and J. He, J. Appl. Physics, 98, 074501 (2005). link
  • J. He, Z. Suo, T.N. Marieb, and J.A. Maiz, Appl. Phys. Lett. 85, 4639 (2004). link


Brain Storm and Carbon Nanotubes

Last year, I attended the course ES139/239 in Division of Engineering and Applied Sciences, Harvard University, the innovation in science and technology. The final project of my group was about carbon nanotube (CNT). In the stage of popping up ideas, we did not consider any feasibility issues, and just used our imagination to create fancy ideas. I was inspired by other guys a lot, felt too excited after the evening brainstorm session, and wrote down the ideas I coined up. Some of them are not nonsense, e.g. replacing Cu by CNT as conductor in integrated circuit (IC). Later on, I find a piece of news in nanotoday (Dec. 2005) that the company Arrowhead Research was to provide $680,000 over two years to Duke University to develop technology for IC based on CNTs. Of course, I am not the first one to come up with this idea. But this means the random imaginative idea is very helpful and sometimes feasible. Another point I learned from this course is to write down at least one idea per day. Keep doing this, then you have a large pool of ideas. One year later, you have 365 ideas. Don’t expect every idea to be useful. Even if just one or two of them are great, it is worthy doing. Imagine that if the future technology originated from one of your ideas, you will contribute the society and feel fullness of ecstasy. If you can realize your idea, you can be a millionaire or billionaire, and then lie on the beach of Caribbean to enjoy the sunshine.

Split singularities and the competition between crack penetration and debond at a bimaterial interface

Zhen Zhang and Zhigang Suo

For a crack impinging upon a bimaterial interface at an angle, the singular stress field is a linear superposition of two modes, usually of unequal exponents, either a pair of complex conjugates, or two unequal real numbers. In the latter case, a stronger and a weaker singularity coexist (known as split singularities). We define a dimensionless parameter, called the local mode mixity, to characterize the proportion of the two modes at the length scale where the processes of fracture occur. We show that the weaker singularity can readily affect whether the crack will penetrate, or debond, the interface.

A new home for mechanics researchers

Zhigang is really a master of good ideas. He learned the new technology from his son months ago, and then so many good ideas have been popping up in the mechanics community. Google group was the first trial, then google blog, wikepedia, etc. Now even fancier, iMech. I dreamed before, if I had money, I would buy a series of products by Apple. Now and in the future, I wish I can obtain iMech for free. I wish it has the quality as other products of i*** by Apple, but not as expensive as those. Good news is that the iMech is made by Zhigang, not Apple.

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