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EM 397 Term Paper: Stress-Induced Voiding in Dual-Damascene Cu Interconnects

Stress-induced voiding (SIV) is investigated in Cu-based, deep-submicron, dual damascene technology. Two failure modes are revealed by TEM failure analysis. For one mode, voids are formed under the via when the via connects a wide metal lead below it. For the via which is instead under a wide metal line, voids are formed right above the via bottom. The void source results from the supersaturated vacancies which develop when Cu is not properly annealed after electroplating and before being constrained by dielectrics. The driving force comes from the stress built up due to grain growth and the thermal expansion mismatch (CTE) between Cu interconnect and dielectrics. A diffusion model is introduced to investigate the voiding mechanism primarily for the vias connected to wide metal leads.

References:

1. E. T. Ogawa, J. W. MePherson, J. A. Rosal, K. J. Dickerson, T. C. Chiu, L. Y. Tsung, M. K. Jain, T. D. Bonifield, J. C. Ondrusek, and W. R. McKee, “Stress-Induced Voiding Under Vias Connected To Wide Cu Metal Leads”, 2002 IEEE International Reliability Physics Symposium Proceedings, 2002, pp. 312-321.

2. M. Kawano, T. Fukase, Y. Yamamoto, T. Ito, S. Yokogawa, H. Tsuda, Y. Kunimune, T. Saitoh, K. Ueno, and M. Sekine, “Stress Relaxation in Dual-damascene Cu Interconnects to Suppress Stress-Induced Voiding”, Proceedings of the 2003 International Interconnect Technology Conference, 2003.

3. J. M. Paik, J. K. Jung, and Y. C. Joo, “The Dielectric Material Dependence of Stress And Stress Relaxation on The Mechanics of Stress-Voiding of Cu Interconnects”, 2005 IEEE International Reliability Physics Symposium Proceeding, pp. 195-202.

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Comments

Dr. Huang,

I'm sorry that I made a mistake when I tried to update the references. I deleted the whole stuff so that your comments were also deleted by mistake and it can not be undone. I also update the term paper as a PDF attachment.

Sorry for the mistake and thanks for your suggestions!

 

Lijuan

 

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