A new Method for Detection of Degradation in Die-Attach Materials by In-Situ-Health Monitoring of Thermal Properties

The application of electronic products is established in many fields of everyday life, for example in automotive industry, medical or communication technology. This leads to the necessity of investigation of safety and reliability of such components. During lifetime testing of the electronic component different loads and mechanisms can lead to degradation and failure. For die attach materials these failures can be cohesive or adhesive in their nature. In order to find an estimate for the quantitative amount of die attach degradation the modification or change of thermal behaviour can give an indication ([3], [4], [5]). In [3] the temperature versus time measurement demonstrates the effect of die-attach degradation on thermal impedance through the life time of a MOSFET package. This effect has also been applied to the transient thermal characterisation of a 48-lead TSSOP package [6]. John W. Sofia [7] presents in his paper the thermal step-response, traditionally known as “transient response” or “heating curve”, measures the junction temperature after an abrupt step-change in internal power dissipation. As the step-change in power heats the device from an initially unpowered equilibrium condition to powered, steady state equilibrium, the resulting thermal data stream embodies the transient and equilibrium thermal characteristics of the device under test. He illustrates an example of mock empirical data for the step response of a mechanical system. A hypothetical model consisting of a mass, spring, and damper is presented. He researches junction-to-case step response for a MOSFET TO-247 device with case temperature measured under the die. The difference in thermal expansion coefficient (CTE) between the silicon die and packaging substrate in a chip package causes concentrated stress field around the edges and corner of silicon die during assembly, testing and services. The concentrated stresses result in void and crack growth during lifetime. Therefore, we will study the thermal influence of interface cracks (delaminations) around the edges or corners of a silicon die for a COB package. The goal of our investigations is to find a direct relationship between thermal impedance Zth and size of degradation in the die attach. First this is analysed by simulation in order to prove feasibility and optimize the method with respect to sensitivity. In the next step the simulation results are verified by an experiment.