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Fracture at corners or edges in bi-material systems

Xuejun Fan's picture

Dr. Suo's group is recently studying the sharp features such as corners or edges. It becomes important to characterize fracture behaviors at corners and edges in microelectronics.

I have two questions,

1. For a corner problem, since the shear stress singularity is weaker, the fracture toughness is a single value. However, when an interface crack is formed, the fracture toughness depends on mixty ratio. How to link these two descirption and make consistent;

2. For a corner in a bimaterial where TWO interfaces are involved, will still a single fracture parameter is enough to describe the crack iniation?

I attach a paper for details of problem statements.

PDF icon IEEE CPT 2001 -Fan.pdf196.62 KB


Liu ZhuangJian's picture


Very glad to see you here.


As for the first question, have a look at this reference:

  • Nakamura, T., “Three-Dimensional Stress Fields of Elastic Interface Cracks”, Journal of Applied Mechanics, 58 (1991) 939-946.


Hi, Xuejun,

You are right. We are now studying the singularities around the sharp features. I was preparing my thesis defense last week and sorry for a late response to your post.

We have just studied the flip-chip package. About the questions you raised, maybe I can try to make a comment.

1). For a corner in homogeneous material, the shearing mode is quite weak, as you pointed out. But for a bimaterial corner, e.g. 90 deg wedge configuration in flip-chip package as in your paper, there are usually two singularities exponents, one stronger, the other weaker. But because there is no symmetry, so we cannot say opening mode or shearing mode anymore. And also both of two singularity values are quite strong, e.g. for die/FR4, they are 0.499 and 0.318. So we have to consider both modes.

2). For the corner in flip-chip package, we know the underfill and fillet height play very important role in reliability. If they are thick enough, they relieve the stress concentration, acting as a buffer layer. Maybe this buffering effect is tapering due to the miniaturization of solder joints and the associated gap between silicon die and package substrate.

3) what do you mean by “two interfaces are involved”? Do you mean “the interface crack around a bimaterial corner”?


Here is the link of my current post on the topic of interfacial delamination and chip-package interaction. Please comment and let’s discuss more.



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