strained silicon

In practice, the SiN stripes or pads are periodically patterned on silicon, so the spacing effect on dislocation injection from sharp features deserves attention. As in Figure 1, the SiN stripes with residue stress, of width L and thickness h, are periodically patterned with spacing S. In the numerical calculation, we take shear modulus and Poisson’s ratio of Si3N4 to be 54.3 GPa and 0.27, and those of silicon 68.1GPa and 0.22, the same as in Ref.[1].

Electronic active device is built on the strained silicon-on-insulator (sSOI), e.g. strained Si layer on oxide, which in turn is bonded on bulk silicon wafer. Because no misfit dislocation can exist in strained silicon layer any more, will the dislocation be generated during later processing and operation? If there are still lots of dislocations in the strained silicon layer, where do they come from? Is there any experimental work to discover the dislocation nucleation sites? I guess they will nucleate from the triple junctions of gate-sSOI-cap, because the stress is singular in the triple junction. But I am not sure. So I want to know something about the experimental observations.