Job description for Internship as a Flexible Display Technologist
Job Summary:
In this position, you will play a critical role in developing and assessing new display technologies in for possible use in Apple products, crafting new designs and intellectual property for Apple, and interacting with multiple partners across the company and with technology and product suppliers to Apple.
Key Qualifications:
There are many job positions on hardware reliability due to the success of on xbox Kinect. The following is the typical description. Please check out http://www.microsoft-careers.com for more.
Date: Dec 22, 2010
On Aug 10, 2009, Semiconductor International (SI) Newsbreak published a report on my work in AMD about 3D fracture study of underfill delamination as the top story in that issue. I have never imagined that. Except the pleasure I received from this good news, I wonder if this work is also interesting to iMechanica community. For that reason, I attach here the SI news report and the original paper published on ITherm2008 Proceedings. Welcome any comments and thoughts.
A friend just forwarded me the following link:
http://math.rejecta.org/
quote:
"
Rejecta Mathematica is a new, open access, online journal that publishes only papers that have been rejected from peer-reviewed journals (or conferences with comparable review standards) in the mathematical sciences. We are currently seeking submissions for our inaugural issue.
About Rejecta Mathematica
In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and services. The concentrated stresses result in delamination on many interfaces on several levels of structures, in various length scales from tens of nanometers to hundreds of micrometers. A major challenge to model flip-chip packages is the huge variation of length scales, the complexity of microstructures, and diverse materials properties. In this paper, we simplify the structure to be silicon/substrate with wedge configuration, and neglect the small local features of integrated circuits. This macroscopic analysis on package level is generic with whatever small local features, as long as the physical processes of interest occur in the region where the concentrated stress field due to chip-packaging interaction dominates. Because it is the same driving force that motivates all of the flaws. Therefore, the different interface cracks with same size and same orientation but on different interfaces should have similar energy release rates provided that the cracks are much smaller than the macroscopic length. We calculate the energy release rate and the mode angle of crack on the chip-package interface based on the asymptotic linear elastic stress field. In a large range of crack length, the asymptotic solution agrees with finite element calculation very well. We discuss the simplified model and results in context of real applications. In addition, we find that the relation of energy release rate G and crack length a is not power-law since local mode mixity is dependent of crack length a. Therefore, the curve of G~a can be wavy and hardly goes to zero even if crack length a goes to atomically small. The local mode mixity plays an important role in crack behavior.
Stresses inevitably arise in a microelectronic device due to mismatch in coefficients of thermal expansion, mismatch in lattice constants, and growth of materials. Moreover, in the technology of strained silicon devices, stresses have been deliberately introduced to increase carrier mobility. A device usually contains sharp features like edges and corners, which may intensify stresses, inject dislocations into silicon, and fail the device. On the basis of singular stress fields near the sharp features, this letter describes a method to obtain conditions that avert dislocations.