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Rui Huang's picture

Journal Club Theme of March 15: Impact of Chip-Package Interaction on Reliability of Copper/Low k Interconnects and Beyond

Fri, 2008-03-14 23:20 - Rui Huang
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interconnect
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reliability
Integrated Structures
microelectronics

The exponential growth in integrated device density has yielded high-performance microprocessors containing almost 1 billion transistors per chip for the current 65 nm technology. Continuous scaling of the devices and performance requires innovations in materials, processes, and designs for both back-end-of-line (BEoL) interconnects and packaging structures. Mechanical reliability has been a limiting factor for implementation of new materials and processes.

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Xiao Hu Liu's picture

Delamination in Patterned Films

Tue, 2006-11-14 11:57 - Xiao Hu Liu
industry
thin film
fracture
fracture mechanics
crack
debond
interconnect
delamination

When the dielectric constant of an insulator in an interconnect is reduced, mechanical properties are often compromised, giving rise to significant challenges in interconnect integration and reliability. Due to low adhesion of the dielectric an interfacial crack may occur during fabrication and testing. To understand the effect of interconnect structure, an interfacial fracture mechanics model has been analyzed for patterned films undergoing a typical thermal excursion during the integration process.

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Xiao Hu Liu's picture

Pattern Effect on Low-k Channel Cracking

Thu, 2006-11-02 21:23 - Xiao Hu Liu
research
thin film
interconnect
channel crack

Low dielectric constant (low-k) is achieved often at the cost of degraded mechanical properties, making it difficult to integrate the dielectric in the back end of line (BEOL) and to package low-k chips. Development of low-k technology becomes costly and time-consuming. Therefore, more frequently than before, people resort to modeling to understand mechanical issues and avoid failures. In this paper we present three multilevel patterned film models to examine channel cracking in low-k BEOL. The effects of copper features, caps and multilevel interconnects are investigated and their implications to BEOL fabrication are discussed.

Low-k BEOL Mechanical Modeling
Liu, Xiao Hu; Lane, Michael W; Shaw, Thomas M; Liniger, Eric G; Rosenberg, Robert R; Edelstein, Daniel C
Advanced Metallization Conference 2004 (AMC 2004); San Diego, CA and Tokyo; USa and Japan; 19-21 Oct. 2004 and 28-29 Sept. 2004. pp. 361-367. 2005

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Joost Vlassak's picture

The Effect of Water Diffusion on the Adhesion of Organosilicate Glass Film Stacks

Wed, 2006-09-20 10:30 - Joost Vlassak
industry
thin film
adhesion
fracture
interconnect
vlassak_research_group

Ting Y. Tsui, Andrew J. McKerrow, and Joost J. Vlassak

Published in the Journal of The Mechanics and Physics of Solids, 54 (5), 887-903 (2006)

Abstract – Organosilicate glass (OSG) is a material that is used as a dielectric in advanced integrated circuits. It has a network structure similar to that of amorphous silica where a fraction of the Si-O bonds has been replaced by organic groups. It is well known from prior work that OSG is sensitive to subcritical crack growth as water molecules in the environment are transported to the crack tip and assist in rupturing Si-O bonds at the crack tip. In this study, we demonstrate that exposure of an OSG containing film stack to water prior to fracture results in degradation of the adhesion of the film stack. This degradation is the result of the diffusion of water into the film stack. We propose a quantitative model to predict adhesion degradation as a function of exposure time by coupling the results of independent subcritical crack growth measurements with diffusion concentration profiles. The model agrees well with experimental data and provides a novel method for measuring the water diffusion coefficient in film stacks that contain OSG. This study has important implications for the reliability of advanced integrated circuits.

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Saturated voids in interconnect lines due to thermal strains and electromigration

Thu, 2006-09-14 15:57 - Zhen Zhang
research
suo group research
electromigration
interconnect

Zhen Zhang, Zhigang Suo, Jun He

Thermal strains and electromigration can cause voids to grow in conductor lines on semiconductor chips. This long-standing failure mode is exacerbated by the recent introduction of low-permittivity dielectrics. We describe a method to calculate the volume of a saturated void (VSV), attained in a steady state when each point in a conductor line is in a state of hydrostatic pressure, and the gradient of the pressure along the conductor line balances the electron wind. We show that the VSV will either increase or decrease when the coefficient of thermal expansion of the dielectric increases, and will increase when the elastic modulus of the dielectric decreases. The VSV will also increase when porous dielectrics and ultrathin liners are used. At operation conditions, both thermal strains and electromigration make significant contributions to the VSV. We discuss these results in the context of interconnect design.

This has been published and the related references are listed here:

  • Z. Zhang, Z. Suo, and J. He, J. Appl. Physics, 98, 074501 (2005). link
  • J. He, Z. Suo, T.N. Marieb, and J.A. Maiz, Appl. Phys. Lett. 85, 4639 (2004). link

 

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