Zhen Zhang and Zhigang Suo (Harvard), Jun He (Intel)
Attached is a set of slides presented at ASME Congress, 10 November 2006. Thermal strains and electromigration can cause voids to grow in conductor lines on semiconductor chips. This long-standing failure mode is exacerbated by the recent introduction of low-permittivity dielectrics. We describe a method to calculate the volume of a saturated void (VSV), attained in a steady state when each point in a conductor line is in a state of hydrostatic pressure, and the gradient of the pressure along the conductor line balances the electron wind. We show that the VSV will either increase or decrease when the coefficient of thermal expansion of the dielectric increases, and will increase when the elastic modulus of the dielectric decreases. The VSV will also increase when porous dielectrics and ultrathin liners are used. At operation conditions, both thermal strains and electromigration make significant contributions to the VSV. We discuss these results in the context of interconnect design.
