User login


You are here

Xiao Hu Liu's blog

Xiao Hu Liu's picture

ASME 2015 International Technical Conference and Exhibition on Packaging (InterPACK 2015) July 6-9, 2015 The Fairmont San Francisco Hotel, San Francisco, California

ASME 2015 International Technical Conference and Exhibition on Packaging (InterPACK 2015) will be in the Fairmont San Francisco Hotel, San Francisco, California from July 6-9, 2015. You are invited to submit paper to the topic on Advances in Interconnect Technologies at the InterPACK 2015. Please see the attachment of call for paper and note the abstract deadline of Dec. 8, 2014.


Xiao Hu Liu's picture

CFD analyst opening

Please apply online. Do not contact me; I do not work in the company.


Xiao Hu Liu's picture

Position for expert FEA analyst available at Dallas area, Texas

Please apply online. Do not contact me; I do not work in the company.

The Research and Computer Aided Engineering group at Carrollton Technology Center of Halliburton is looking for an expert FEA analyst at principal engineer level. This position requires

1) Extensive experience with nonlinear finite element analysis and fundamental understanding and knowledge of Solid Mechanics.

Xiao Hu Liu's picture

The piezoelectronic transistor: A nanoactuator-based post-CMOS digital switch with high speed and low power

A review article of our research at IBM TJ Wason Research Center in piezoelectronic transistor, an exploratory device beyond silicon, is published in MRS Bulletin, Volume 37, Issue 11, November 2012, pp 1071-1076. Your future computer may depend even more on the mechanics.


Xiao Hu Liu's picture

Job Opening at IBM Microelectronics: Semiconductor Process Integration Engineering Professinal

There are several openings for semiconductor process integration at IBM Microelectronics. The reqiured background is quite broad, specifically mechanical engineering background, reliability, failure analysis and modeling with experience in BEOL process and integration. To see more details and to apply online, please click the link below.


Xiao Hu Liu's picture

Packaging Mechanical Engineer at Hopewell Junction, NY, IBM Microelectronics Division

Packaging mechanical engineers conduct simulation of electronic packages
to optimize package design for compatibility with assembly processes
and for reliable operation in end user systems such as servers, game
consoles and network switches. Simulation is conducted using commercial
finite element software such as ANSYS or ABAQUS to predict package
component stresses and strains. Simulations are verified by measurements
of warpage and stresses / strains in the packages using Digital image
contrast, strain gages, capacitance meters, etc. Package material
properties such as coefficient of thermal expansion, Poisson ratio and
modulus that are required for simulation are measured using specialized
mechanical equipment. Thus, familiarity with numerical simulation

Xiao Hu Liu's picture

Open Position: 2011 Summer Internship at IBM TJ Watson Research Center, Yorktown Heights, NY


We are looking for an intern to join us this summer at IBM TJ Watson Research Center. You can find the job description at the link below. Please send your resume to apply for it there. More specifically, a background in molecular dynamics is required, and an experience of running open source MD code on supercomputer is preferred. The job will be filled quickly, and you are advised to apply as soon as possible.

Xiao Hu Liu's picture

Delamination in Patterned Films

When the dielectric constant of an insulator in an interconnect is reduced, mechanical properties are often compromised, giving rise to significant challenges in interconnect integration and reliability. Due to low adhesion of the dielectric an interfacial crack may occur during fabrication and testing. To understand the effect of interconnect structure, an interfacial fracture mechanics model has been analyzed for patterned films undergoing a typical thermal excursion during the integration process.

Xiao Hu Liu's picture

Pattern Effect on Low-k Channel Cracking

Low dielectric constant (low-k) is achieved often at the cost of degraded mechanical properties, making it difficult to integrate the dielectric in the back end of line (BEOL) and to package low-k chips. Development of low-k technology becomes costly and time-consuming. Therefore, more frequently than before, people resort to modeling to understand mechanical issues and avoid failures. In this paper we present three multilevel patterned film models to examine channel cracking in low-k BEOL. The effects of copper features, caps and multilevel interconnects are investigated and their implications to BEOL fabrication are discussed.

Low-k BEOL Mechanical Modeling
Liu, Xiao Hu; Lane, Michael W; Shaw, Thomas M; Liniger, Eric G; Rosenberg, Robert R; Edelstein, Daniel C
Advanced Metallization Conference 2004 (AMC 2004); San Diego, CA and Tokyo; USa and Japan; 19-21 Oct. 2004 and 28-29 Sept. 2004. pp. 361-367. 2005

Subscribe to RSS - Xiao Hu Liu's blog

Recent comments

More comments


Subscribe to Syndicate