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thin films

Journal Club Theme of March 2009: Mechanics Issues in Nanocapacitors and Ramifications for Energy Storage

Submitted by Pradeep Sharma on
research
thin films
dielectrics
nanocapacitors

Next generation advances in energy storage for nanoelectronics, micro and nanosensors among others, require capacitors fabricated at the nanoscale. High dielectric constant materials such as ferroelectrics are important candidates for those. Consider the following: the expected capacitance of a 2.7 nm SrTiO3 thin film is 1600 fFmicro-m-2. What is the likely value in reality? 258 fFmicrom-2! This dramatic drop in capacitance is attributed to the so-called "dead layer" effect.

Determining the elastic modulus and hardness of an ultra-thin film on a substrate using nanoindentation

Submitted by Li Han on
research
thin films
nanoindentation
vlassak_group_research
Elastic properties
Substrate effect

Abstract – A data analysis procedure has been developed to estimate the contact area in an elasto-plastic indentation of a thin film bonded to a substrate. The procedure can be used to derive the elastic modulus and hardness of the film from the indentation load, displacement, and contact stiffness data at indentation depths that are a significant fraction of the film thickness. The analysis is based on Yu’s elastic solution for the contact of a rigid conical punch on a layered half-space and uses an approach similar to the Oliver-Pharr method for bulk materials.

Post-Doc position on stresses and adhesion in multilayers (France)

Submitted by Etienne Barthel on
job
adhesion
thin films
experimental
residual stresses
XRay diffraction

Please note that a post-doc position on stresses and adhesion in optical multilayers is open. The position is for 2-years shared between SVI (Paris) and Phymat (Poitiers).

Link to a virus-free MS Word description of the position:

http://www.saint-gobain-recherche.com/svi/en/image_merethif_position.html

For further details and applications (cover letter, CV, statement of research interests):

Thin films: wrinkling vs buckle-delamination

Submitted by Rui Huang on
research
thin films
buckling
wrinkling
R. Huang Group Research

H. Mei, J.Y. Chung, H.-H. Yu, C.M. Stafford, and R. Huang, Buckling modes of elastic thin films on elastic substrates. Applied Physics Letters 90, 151902 (2007).

Two modes of thin film buckling are commonly observed, one with interface delamination (e.g., telephone cord blisters) and the other with no delamination (i.e., wrinkling). Which one would occur for your film?

Symposium: Plasticity and Damage Size Effects at the Micron and Nano Length Scales

Submitted by Rashid K. Abu Al-Rub on
conference
Plasticity
thin films
size effect
damage
nonlocal theory
strain gradient
length scale

The SES 2007 Conference, Oct. 21-24, 2007, Texas A&M University campus in College Station, Texas, home to the George Bush Presidential Library and Museum.

 Symposium: Plasticity and Damage Size Effects at the Micron and Nano Length Scales

High ductility of a metal film adherent on a polymer substrate

Submitted by Yong Xiang on
research
fracture
thin films
deformable eclectronics
high ductility

In recent development of deformable electronics, it has been noticed that thin metal films often rupture at small tensile strains. Here we report experiments with Cu films deposited on polymeric substrates, and show that the rupture strains of the metal films are sensitive to their adhesion to the substrates. Well-bonded Cu films can sustain strains up to 10% without appreciable cracks, and up to 30% with discontinuous microcracks. By contrast, poorly bonded Cu films form channel cracks at strains about 2%. The cracks form by a mixture of strain localization and intergranular fracture.

EM 397 Term Paper: Stress-Induced Voiding in Dual-Damascene Cu Interconnects

Submitted by Lijuan Zhang on
University of Texas at Austin
Fall 2006
thin films
EM 397
term paper

Stress-induced voiding (SIV) is investigated in Cu-based, deep-submicron, dual damascene technology. Two failure modes are revealed by TEM failure analysis. For one mode, voids are formed under the via when the via connects a wide metal lead below it. For the via which is instead under a wide metal line, voids are formed right above the via bottom. The void source results from the supersaturated vacancies which develop when Cu is not properly annealed after electroplating and before being constrained by dielectrics. The driving force comes from the stress built up due to grain growth and the thermal expansion mismatch (CTE) between Cu interconnect and dielectrics. A diffusion model is introduced to investigate the voiding mechanism primarily for the vias connected to wide metal leads.

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